Biomedical subjects

Jakub Kedzierski

Publications and source records attributed to Jakub Kedzierski.

3 recordsLinked to original sources

PubMed2006

Low voltage electrowetting using thin fluoroploymer films.

This paper investigates the nonideal electrowetting behavior of thin fluoroploymer films. Results are presented for a three phase system consisting of: (1) an aqueous water droplet containing sodium dodecyl sulfate (SDS), (2) phosphorous-doped silicon topped with SiO2 and an amorphous fluoroploymer (aFP) insulating top layer on which the droplet is situated, and (3) a dodecane oil that surrounds the droplet. The presented measurements indicate that the electrowetting equation is valid down to a 6 nm thick aFP film on a 11 nm thick SiO2. At this dielectric thickness, a remarkable contact angle change of over 100 degrees can be achieved with an applied voltage less than 3 V across the system. The data also shows that for this water/surfactant/oil system, contact angle saturation is independent of the electric field, and is reached when the surface energy of the solid-water interface approaches zero.

Journal Article↗

PubMed2006

Engineering the electrocapillary behavior of electrolyte droplets on thin fluoropolymer films.

This study presents methods for engineering the electrocapillary behavior of fluoropolymer surfaces through the use of surfactants and an external insulating liquid. By the scaling of the appropriate surface energies, electrocapillary behavior is obtained at a record low voltage, with contact angle changes in excess of 100 degrees at 4 V. A consistent description of electrocapillary saturation is presented, identifying three separate regimes: breakdown, thermodynamic instability, and relaxation. Methods for identifying and mitigating some of the saturation behaviors are discussed. Finally, the parameters influencing the observed voltage of zero charge are summarized.

Journal Article↗

PubMed2004

Silicon device scaling to the sub-10-nm regime.

In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

Journal Article↗