A hardware efficient cascadable chip set for ANN's with on-chip backpropagation.

T Lehmann

doi:10.1142/s0129065793000298

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A hardware efficient cascadable chip set for ANN's with on-chip backpropagation.

T Lehmann

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Abstract

In this paper, an analogue, cascadable, CMOS chip set for artificial neural networks is presented. The chip set (a synapse chip and a neuron chip) offer on-chip back-propagation learning in a fully parallel, layered, feedforward network of arbitrary size and topology. The learning scheme is implemented with no extra circuits at the synapse sites (compared to the system without the learning scheme) and extra circuits of a complexity only about the same as the neurons at the neuron sites. Also, no additional wiring is required by the learning scheme. Measurements on an experimental chip set are presented.

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Algorithms Artificial Intelligence Computers Computers, Analog Neural Networks, Computer Neurons Semiconductors Synapses Journal Article Research Support, Non-U.S. Gov't

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T Lehmann. 1993. A hardware efficient cascadable chip set for ANN's with on-chip backpropagation.. https://doi.org/10.1142/s0129065793000298

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